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Integrated Circuit Systems, Inc.
ICS950508
Programmable Timing Control HubTM for PII/IIITM
Recommended Application: 810/810E/815 and 815 B-Step type chipset Output Features: * 2 - CPUs @ 2.5V * 13 - SDRAM @ 3.3V * 3 - 3V66 @ 3.3V * 8 - PCI @3.3V * 1 - 24/48MHz@ 3.3V * 1 - 48MHz @ 3.3V fixed * 1 - REF @3.3V, 14.318MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter: <250ps * IOAPIC Output Jitter: <500ps * 48MHz, 3V66, PCI Output Jitter: <500ps * Ref Output Jitter. <1000ps * CPU Output Skew: <175ps * PCI Output Skew: <500ps * 3V66 Output Skew <175ps * For group skew timing, please refer to the Group Timing Relationship Table.
VDDREF X1 X2 GND GND 3V66_0 3V66_1 3V66_2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1 *FS1/PCICLK1 1 *SEL24_48#/PCICLK2 GND PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GND Vtt_PWRGD/PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GND
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FS4 * VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GND GND SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GND SDRAM6 SDRAM7 SDRAM_F VDDSDR GND 24_48MHz/FS2* 48MHZ/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 GND
1
56-Pin 300-mil SSOP
1. These pins will have 1.5 to 2X drive strength. * Internal Pull-up resistor of 120K to VDD
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
ICS950508
48MHz 24_48MHz
REF0
CPU DIVDER
2
CPUCLK (1:0)
SDRAM DIVDER
12
SDRAM (11:0) SDRAM_F
FS(4:0) PD# SEL24_48# Vtt_PWRGD SDATA SCLK
Control Logic Config. Reg.
IOAPIC DIVDER
IOAPIC
PCI DIVDER
8
PCICLK (7:0)
3V66 DIVDER
3
3V66 (2:0)
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Integrated Circuit Systems, Inc.
ICS950508
General Description
The ICS950508 is a single chip clock solution for desktop designs using the 810/810E, 815 and 815 B-Step style chipset. It provides all necessary clock signals for such a system. The ICS950508 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
Pin Description
PIN NUMBER 1, 9, 10, 18, 25, 32, 33, 37, 45 2 3 4, 5, 14, 21, 28, 29, 36, 41, 49 8, 7, 6 11 PIN NAME VDD X1 X2 GND 3V66 (2:0) PCICLK0 FS0 PCICLK11 12 FS1 13 20, 19, 17, 16, 15 SEL_24_48# PCICLK21 PCICLK (7:3) PD# 22 Vtt_PWRGD 23 24 34 35 38 48, 46, 47, 44, 43, 42, 40, 39, 31, 30, 27, 26 50 51, 52 53, 55 54 56
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TYPE PWR IN OUT PWR OUT OUT IN OUT IN IN OUT OUT IN 3 . 3 V p ow e r s u p p l y
DESCRIPTION
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF) Ground pins for 3.3V supply 3.3V Fixed 66MHz clock outputs for HUB 3.3V PCI clock output, with Synchronous CPUCLKs L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V PCI clock output, with Synchronous CPUCLKs L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . Logic input to select output. 3.3V PCI clock output, with Synchronous CPUCLKs 3.3V PCI clock outputs, with Synchronous CPUCLKs Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the V C O a n d t h e c r y s t a l a r e s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s. This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD goes high the frequency select w i l l b e l a t c h e d a t p ow e r o n ; t h e r e a f t e r t h e p i n i s a n a s y n c h r o n o u s active low power down pin. Clock pin for I2C circuitr y 5V tolerant Data pin for I2C circuitr y 5V tolerant L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V Fixed 48MHz clock output for USB L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V 24_48MHz output, selectable through pin 13, default is 24MHz. 3 . 3 V S D R A M o u t p u t c a n b e t u r n e d o f f t h r o u g h I 2C 3 . 3 V o u t p u t . A l l S D R A M o u t p u t s c a n b e t u r n e d o f f t h r o u g h I 2C Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. Output frequency der ived from FS p i n s. 2.5V power suypply for CPU, IOAPIC 2.5V clock outputs r unning at 16.67MHz. L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n . 3.3V, 14.318MHz reference clock output.
IN IN I/O IN OUT IN OUT OUT OUT PWR OUT PWR OUT IN OUT
SCLK SDATA FS3 48MHz FS2 24_48MHz SDRAM_F SDRAM (11:0) GNDL CPUCLK (1:0) VDDL IOAPIC FS4 REF01
2
Integrated Circuit Systems, Inc.
ICS950508
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
*See notes on the following page.
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Integrated Circuit Systems, Inc.
ICS950508
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK SDRAM MHz MHz FS4 FS3 FS2 FS1 FS0 3V66 MHz PCICLK MHz 33.21 30.00 33.40 34.17 35.00 37.50 40.00 41.50 33.21 30.00 33.41 34.33 35.00 36.67 38.33 66.66 33.21 41.67 33.41 34.25 35.00 36.25 37.50 40.00 33.21 41.67 33.41 34.25 35.00 36.25 37.50 40.00 IOAPIC MHz 16.61 15.00 16.70 17.08 17.50 18.75 20.00 20.75 16.61 15.00 16.70 17.17 17.50 18.33 19.17 33.33 16.61 20.83 16.70 17.13 17.50 18.13 18.75 20.00 16.61 20.83 16.7 17.13 17.50 18.13 18.75 20.00
PWD
Bit (2,7:4)
Bit 3 Bit 1 Bit 0
Notes: 1. Default
0 0 0 0 0 66.43 99.65 66.43 0 0 0 0 1 60.00 90.00 60.00 0 0 0 1 0 66.80 100.20 66.80 0 0 0 1 1 68.33 102.50 68.33 0 0 1 0 0 70.00 105.00 70.00 0 0 1 0 1 75.00 112.50 75.00 0 0 1 1 0 80.00 120.00 80.00 0 0 1 1 1 83.00 124.50 83.00 0 1 0 0 0 99.65 99.65 66.43 90.00 60.00 0 1 0 0 1 90.00 0 1 0 1 0 100.23 100.23 66.84 0 1 0 1 1 103.00 103.00 68.67 0 1 1 0 0 105.00 105.00 70.00 0 1 1 0 1 110.00 110.00 73.33 0 1 1 1 0 115.00 115.00 76.67 0 1 1 1 1 200.00 200.00 133.33 1 0 0 0 0 132.86 132.86 66.43 1 0 0 0 1 166.67 166.67 83.34 133.64 133.64 66.82 1 0 0 1 0 1 0 0 1 1 137.00 137.00 68.50 1 0 1 0 0 140.00 140.00 70.00 1 0 1 0 1 145.00 145.00 72.50 1 0 1 1 0 150.00 150.00 75.00 1 0 1 1 1 160.00 160.00 80.00 1 1 0 0 0 132.86 99.65 66.93 1 1 0 0 1 166.67 125.00 83.34 1 1 0 1 0 133.64 100.23 66.82 1 1 0 1 1 137.00 102.75 68.50 1 1 1 0 0 140.00 105.00 70.00 1 1 1 0 1 145.00 108.75 72.50 1 1 1 1 0 150.00 112.50 75.00 1 1 1 1 1 160.00 120.00 80.00 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,7:4 0- Normal 1- Spread spectrum enable 0.35% Center Spread 0- Running 1- Tristate all outputs
Note 1
0 1 0
at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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Integrated Circuit Systems, Inc.
ICS950508
Byte 1: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 35 34 38
PWD X X X 1 1 1 1 1
Description Readback FS3# Readback FS0# Readback FS2# 24MHz (Reserved) 48MHz (Reserved) SDRAM_F
Byte 2: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 39 40 42 43 44 46 47 48
PWD 1 1 1 1 1 1 1 1
Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 17 16 15 13 12 11
PWD 1 1 1 1 1 1 1 1
Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 4: Output Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Pin# 8 6 7 54 51 52
PWD 1 1 1 X 1 X 1 1
Description 3V66_2 3V66_0 3V66_1 Readback FS4# IOAPIC Readback FS1# CPUCLK1 CPUCLK0
5
Integrated Circuit Systems, Inc.
ICS950508
Byte 5: Output Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 26 27 30 31
PWD X 1 1 0 1 1 1 1
Description Readback (SEL24, 48#)# (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8
Byte 6: Vendor ID Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bi t 0
Name Vendor ID2 Vendor ID1 Vendor ID0
PWD X X X X X 0 0 1
Description (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ICS vendor ID is 001 as in number 1 in frequency timing generation.
Byte 7: Revision ID and Device ID Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Revision ID2 Revision ID1 Revision ID0 Device ID4 Device ID3 Device ID2 Device ID1 Device ID0
PWD Description 0 0 0 Device ID and Revision ID values will be 0 based on individual device and it's revisio, "01h" in this case. 0 0 0 1
Byte 8: Byte Count Read Back Register
Bit Bit 7 Bi t 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bi t 1 Bi t 0
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Name Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
PWD Description 0 0 0 Note: Writing to this register will configure 0 byte count and how many bytes will be read back, default is 0FH = 15 bytes. 1 0 0 0
6
Integrated Circuit Systems, Inc.
ICS950508
Byte 9: Watchdog Timer Count Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to X * 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16 * 290ms = 4.6 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit Bit 7 Bi t 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Program Enable WD Enable WD Alarm SF4 SF3 SF2 SF1 SF0
PWD 0 0 0 0 0 0 0 0
Description Programming Enable bit 0 = no programming. Frequencies are selected by HW latches or Byte0 1 = enable all I2C programing. Watchdog Enable bit Watchdog Alarm Status 0 = normal 1= alarm status Watchdog safe frequency bits. Writing to these bits will configure the safe frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Ndiv 8 Mdiv 6 Mdiv 5 Mdiv 4 Mdiv 3 Mdiv 2 Mdiv 1 Mdiv 0
PWD X X X X X X X X
Description N divider bit 8 The decimal respresentation of Mdiv (6:0) corresposd to the reference divider value. Default at power up is equal to the latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Name Ndiv 7 Ndiv 6 Ndiv 5 Ndiv 4 Ndiv 3 Ndiv 2 Ndiv 1 Ndiv 0
PWD X X X X X X X X
Description The decimal representation of Ndiv (8:0) correspond to the VCO divider value. Default at power up is equal to the latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
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Integrated Circuit Systems, Inc.
ICS950508
Byte 13: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SS 7 SS 6 SS 5 SS 4 SS 3 SS 2 SS 1 SS 0
PWD X X X X X X X X
Description The Spread Spectrum (12:0) bit will program the spread precentage. Spread precent needs to be calculated based on the VCO frequency, spreading profile, spreading amount and spread frequency. It is recommended to use the ICS spread programming guide for spread programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved Reserved Reserved SS 12 SS 11 SS 10 SS 9 SS 8
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit 12 Spread Spectrum Bit 11 Spread Spectrum Bit 10 Spread Spectrum Bit 9 Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SD Div 3 SD Div 2 SD Div 1 SD Div 0 CPU Div 3 CPU Div 2 CPU Div 1 CPU Div 0
PWD X X X X X X X X
Description SDRAM clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider. CPU clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 B it 4 B it 3 B it 2 B it 1 B it 0
Name PCI Div 3 PCI Div 2 PCI Div 1 PCI Div 0 AGP Div 3 AGP Div 2 AGP Div 1 AGP Div 0
PWD X X X X X X X X
Description PCI clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 2. Default at power up is latched FS divider. AGP clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to Table 1. Default at power up is latched FS divider.
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Integrated Circuit Systems, Inc.
ICS950508
Byte 17: Output Divider Control Register
Bit Bit 7 Bit 6 Bit 5 B it 4 B it 3 Bit 2 Bit 1 Bit 0
Table 1
Name PCI_INV 3V66_INV SD_INV CPU_INV APIC Div 3 APIC Div 2 APIC Div 1 APIC Div 0
PWD X X X X X X X X
Description PCICLK Phase Inversion bit 3V66 Phase Inversion bit SDRAM Phase Inversion bit CPUCLK Phase Inversion bit IOAPIC clock divider ratio can be configured via these 4 bits individually. For divider selection table refer to table 2. Default at power up is latched FS divider.
Table 2
Div (3:2) Div (1:0) 00 01 10 11
00 /2 /3 /5 /7
01 /4 /6 /10 /14
10 /8 /12 /20 /28
11 /16 /24 /40 /56
Div (3:2) Div (1:0) 00 01 10 11
00 /4 /3 /5 /9
01 /8 /6 /10 /18
10 /16 /12 /20 /36
11 /32 /24 /40 /72
Byte 18: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SD_Skew 0 SD_Skew 1 Reserved Reserved CPU_Skew 1 CPU_Skew 0 Reserved Reserved
PWD Description These 2 bits delay the SDRAM with respect to 1 CPUCLK 0 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps 0 Reserved 0 Reserved These 2 bits delay the CPU clock with respect 1 to all other clocks. 0 00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps 0 Reserved 0 Reserved
Byte 19: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name PCI_Skew 3 PCI_Skew 2 PCI_Skew 1 PCI_Skew 0 3V66_Skew 1 3V66_Skew 0 Reser ved Reser ved
PWD 0 0 1 0 1 0 0 0
Description These 4 bits can change the 3V66 to PCI skew from 1.4ns - 2.9ns. Each binar y increment or decrement of PCI_SKEW (3:0) will increase or decrease the delay of the PCI clocks by 100ps. These 2 bits delay the 3V66 with respect to CPUCLK 00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps Reser ved Reser ved
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Integrated Circuit Systems, Inc.
ICS950508
Byte 20: Group Skew Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reser ved Reser ved Reser ved Reser ved APIC_Skew 3 APIC_Skew 2 APIC_Skew 1 APIC_Skew 0
PWD 0 0 0 0 0 0 1 0
Description Reser ved Reser ved Reser ved Reser ved These 4 bits can change the 3V66 to APIC skew from 1.4ns - 2.9ns. Default at power up is - 2.5ns. Each binar y increment or decrement of APIC_SKEW (3:0) will increase or decrease the delay of the PCI clocks by 100ps.
Byte 21: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name 24/48_Slew 1 24/48_Slew 0 3V66_Slew 1 3V66_Slew 0 APIC_Slew 1 APIC_Slew 0 REF_Slew 1 REF_Slew 0
PWD 0 1 0 1 0 1 0 1
Description 24/48 MHz clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak 3V66 clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak IOAPIC clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak REF clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak
Byte 22: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name SD_F Slew 1 SD_F Slew 0 SD(11:8) Slew 1 SD(11:8) Slew 0 SD(7:4) Slew 1 SD(7:4) Slew 0 SD(3:0) Slew 1 SD(3:0) Slew 0
PWD 0 1 0 1 0 1 0 1
Description SDRAM_F clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak SDRAM (11:8) clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak SDRAM (7:4) clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak SDRAM (3:0) clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak
Byte 23: Slew Rate Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name PCI (7:4) Slew 1 PCI (7:4) Slew 0 PCI (3:0) Slew 1 PCI (3:0) Slew 0 CPU 1 Slew 1 CPU 1 Slew 0 CPU 0 Slew 1 CPU 0 Slew 0
PWD 0 1 0 1 0 1 0 1
Description PCI (7:4) clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak PCI (3:0) clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak CPUCLK 1 clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak CPUCLK 0 clock slew rate control bits. 10 = strong: 11 = normal; 01 = weak
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Integrated Circuit Systems, Inc.
ICS950508
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table1
Group CPU 66MHz SDRAM 100MHz Offset CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to PCI USB & DOT 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns 3.75ns 1.5 3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 SYMBOL VIH VIL I IH I IL1 I IL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB t PZH,t PZH tPLZ,t PZH CONDITIONS MIN 2 VSS - 0.3 -5 -5 -200 TYP MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 100 mA 600 14.318 7 Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs) 1 1 5 6 45 3 3 3 10 10 mA MHz nH pF pF pF mS mS mS nS nS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V;
27
Transition Time Settling Time1
1
Clk Stabilization1 Delay
1
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950508
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP2B Vo=VDD*(0.5) Output Impedance1 RDSN2B Vo=VDD*(0.5) IOH = -1 mA Output High Voltage VOH2B Output Low Voltage VOL2B IOL = 1 mA VOH@MIN = 1 V IOH2B Output High Current VOH@MAX = 2.375V VOL@MIN = 1.2 V IOL2B Output Low Current VOL@MAX =0.3V Rise Time1 tr2B VOL = 0.4 V, VOH = 2.0 V Fall Time1 tf2B VOH = 2.0 V, VOL = 0.4 V 1 Duty Cycle dt2B VT = 1.25 V Skew1 tsk2B VT = 1.25 V VT = 1.25 V, CPU 66, SDRAM 100 CPU 100, SDRAM 100 tjcyc-cyc2B Jitter, Cycle-to-cycle1 CPU 133, SDRAM 100 CPU 133, SDRAM 133 1 Guaranteed by design, not 100% tested in production. MIN 13.5 13.5 2 TYP 15 16.5 2.48 0.04 -60 -7 63 20 0.95 0.85 50 32 200 165 400 180 MAX 45 45 0.4 -27 UNITS V V mA mA ns ns % ps ps
-27 27 0.4 0.4 45
30 1.6 1.6 55 175 250 250 450 250
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP4B Vo=VDD*(0.5) Output Impedance1 RDSN4B Vo=VDD*(0.5) IOH = -5.5 mA Output High Voltage VOH4B Output Low Voltage VOL4B IOL = 9 mA VOH@MIN = 1.4 V IOH4B Output High Current VOH@MAX = 2.5V VOL@MIN = 1.0 V IOL4B Output Low Current VOL@MAX =0.2V Rise Time1 tr4B VOL = 0.4 V, VOH = 2.0 V Fall Time1 tf4B VOH = 2.0 V, VOL = 0.4 V 1 Duty Cycle dt4B VT = 1.25 V Jitter, Cycle-to-cycle1 tjcyc-cyc4B VT = 1.25 V
1
MIN 9 9 2
TYP
MAX 30 30 0.4 -21
UNITS V V mA mA ns ns % ps
-36 36 0.4 0.4 45 0.9 1 50 250 31 1.6 1.6 55 500
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950508
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance1 RDSP3 Vo=VDD*(0.5) Output Impedance1 RDSN3 Vo=VDD*(0.5) Output High Voltage VOH3 IOH = -1 mA Output Low Voltage VOL3 IOL = 1 mA VOH@MIN = 2 V IOH3 Output High Current VOH@MAX = 3.135V VOL@MIN = 1 V IOL3 Output Low Current VOL@MAX =0.4V Rise Time1 tr3 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf3 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 dt3 VT = 1.5 V Skew1 tsk3 VT = 1.5 V Jitter, cycle-to-cycle1 tjcyc-cyc3 VT = 1.5 V
1
MIN 10 10 2.4
TYP
MAX 24 24 0.4 -46
UNITS V V mA mA ns ns % ps ps
-54 54 0.4 0.4 45 1.2 0.9 50 218 225 53 1.6 1.6 55 250 250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1 VO = VDD*(0.5) Output Impedance1 RDSN1 VO = VDD*(0.5) IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 1 dt1 VT = 1.5 V Duty Cycle Skew 1 tsk1 VT = 1.5 V Jitter, Cycle-to-cycle1 tjcyc-cyc1 VT = 1.5 V
1
MIN 12 12 2.4
TYP
MAX 55 55 0.55 -33
UNITS V V mA mA ns ns % ps ps
-33 30 0.4 0.4 45 1.55 1.65 53 94 350 38 2 2 55 175 500
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950508
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%, CL = 10 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output Impedance1 RDSP1 Vo=VDD*(0.5) Output Impedance1 RDSN1 Vo=VDD*(0.5) IOH = -1 mA Output High Voltage VOH1 IOL = 1 mA Output Low Voltage VOL1 VOH@MIN = 1 V IOH1 Output High Current VOH@MAX = 3.135V VOL@MIN = 1.95 V IOL1 Output Low Current VOL@MAX =0.4V Rise Time1 Fall Time1 Duty Cycle1 Skew Jitter, cycle-to-cycle1
1 1
MIN 12 12 2.4
TYP
MAX 55 55 0.55 -33
UNITS V V mA mA ns ns % ps ps
-33 30 38 0.5 0.5 45 1.2 2.1 1 2 51 480 300 2 2.25 2 2.25 55 500 500
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V, PCI0-2 PCI3-7 VOL = 2.4 V, VOH = 0.4 V, PCI0-2 PCI3-7 VT = 1.5 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 24_48MHz, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP5 VO = VDD*(0.5) Output Impedance1 RDSN5 VO = VDD*(0.5) Output High Voltage VOH5 IOH = -1 mA Output Low Voltage VOL5 IOL = 1 mA VOH @ MIN = 1.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL5 Output Low Current VOL @ MAX = 0.4 V Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf5 VOH = 2.4 V, VOL = 0.4 V 1 dt5 VT = 1.5 V Duty Cycle Jitter, cycle-to-cycle1
1
MIN 20 20 2.4
TYP
MAX 60 60 0.4 -23
UNITS V V mA mA ns ns % ps
-29 29 0.4 0.4 45 1 1 53 250 2000 27 4 4 55 500 3000
tjcyc-cyc5
VT = 1.5 V, 24, 48 MHz VT = 1.5 V, Ref clocks
Guaranteed by design, not 100% tested in production.
0470E--04/06/05
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Integrated Circuit Systems, Inc.
ICS950508
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Integrated Circuit Systems, Inc.
ICS950508
Power Down Waveform
0ns 1 25ns 50ns 2
VCO Internal CPU 100MHz 3.3V 66MHz PCI 33MHz APIC 16.7MHz PD# SDRAM 100MHz REF 14.318MHZ 48MHZ
Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
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Integrated Circuit Systems, Inc.
ICS950508
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 16.7MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
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Integrated Circuit Systems, Inc.
ICS950508
N
c
L
INDEX AREA
E1
E
12 D h x 45
a
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 SEE VARIATIONS N 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
N
-C-
56
10-0034
VARIATIONS D mm. MIN MAX 18.31 18.55
D (inch) MIN .720 MAX .730
e
b
SEATING PLANE .10 (.004) C
Reference Doc.: JEDEC Publication 95, M O-118
Ordering Information
ICS950508yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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Integrated Circuit Systems, Inc.
ICS950508
Revision History
Rev. D E Issue Date Description 3/15/2005 Update default values of Bytes 18-20 4/6/2005 Update Byte 13 spread programming information Page # 9-10 8
0470E--04/06/05
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